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| [ak4213] ms0949-e-01 - 1 - 2008/07 general description the ak4213 is an audio mono class-d speaker amplifier with ster eo cap-less headphone amplifier. the ak4213 features analog mixing circuit that allow easy interfacing in mobile phone and portable a/v player designs. the input circuit s upports both of single-ended and diffe rential modes, and headphone supports stereo and mono modes. the speak er amplifier includes alc (automatic level control) circuit which is able to stabilize each output sound levels. the ak4213 is available in csp package (3.0mm x 3.0mm), utilizing less board space t han competitive offerings. feature ? single-ended / differential input ? analog mixing circuit ? analog input volume: +10db to ?20db, 2db step ? p interface: i 2 c bus (ver1.0, 400 khz fast-mode) ? thermal shutdown / short protection circuit ? mono class-d speaker amplifier: - btl output - output power: 1.6w @ 8 , svdd=5v 0.8w @ 8 , svdd=3.6v - thd+n: -65db @ 8 , po = 0.25w, svdd=3.6v - output noise level: 85 vrms - alc (automatic level control) circuit - bypass mode - pop noise free at power-on/off and mute - external filter-less ? stereo cap-less headphone amplifier: - mono / stereo mode - output power: 64mw x 2ch @ 16 , svdd=3.3v, thd+n=-40db - thd+n: -58db @ 16 , po=30mw, svdd=3.3v - output noise level: 24 vrms - output volume: +12db to ?50db, 2db step - pop noise free at power-on/off and mute ? power supply: - analog: 2.6v 3.6v - headphone amplifier: 2.6v 3.6v - speaker amplifier: 3.0v 5.5v - digital interface: 1.6v 3.6v ? ta: ? 4 0 85 c ? package: 29pin csp (3.0mm x 3.0mm, 0.5mm pitch) mono class-d spk-amp with stereo cap-less hp-amp ak4213
[ak4213] ms0949-e-01 - 2 - 2008/07 block diagram serial i/f spp vss1 avdd vcom svdd hpl hpr charge pump pvdd vss3 pvee cp cn pmhpl pmcp tvdd spn vss2 alc lin1/in1 ? rin1/in1+ pmspk vol vol mixo spin pmhpr pmmsp internal oscillator pmvcm lin2/in2 ? rin2/in2+ lin3/in3 ? rin3/in3+ pdn mixing selector pmmhl pmmhr vol vol vol vol vol vol mixing selector mixing selector pmosc pmv1 pmv2 pmv3 rvinp rvinn vcom scl sda test regulator pmvcm figure 1. ak4213 block diagram [ak4213] ms0949-e-01 - 3 - 2008/07 ordering guide AK4213ECB ? 40 +85 c 29pin csp (3.0mm x 3.0mm, 0.5mm pitch) akd4213 evaluation board for ak4213 pin layout a b c e d 5 3 4 1 2 top view f 5 hpr lin3/in3- vcom rin1/in1+ svdd lin1/in1- 4 hpl rin3/in3+ rin2/in2+ spn vss2 spp 3 pvee vss3 pdn lin2/in2- test spin 2 pvdd sda tvdd rvinn rvinp 1 cp cn scl vss1 avdd mixo a b c d e f top view [ak4213] ms0949-e-01 - 4 - 2008/07 pin / function no. pin name i/o function e1 avdd - analog power supply pin d1 vss1 - ground 1 pin e3 test o test pin this pin must be open. d2 tvdd - digital interface power supply pin c1 scl i control data clock pin c2 sda i/o control data input/output pin c3 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, resets and initialization of the control register. the ak4213 must be reset once upon power-up. a1 cp i positive charge pump capacitor terminal pin b1 cn i negative charge pump capacitor terminal pin b2 pvdd - charge pump circuit positive power supply pin b3 vss3 - ground 3 pin a3 pvee o charge pump circuit negative voltage output pin a4 hpl o lch headphone-amp output pin a5 hpr o rch headphone-amp output pin f2 rvinp i receiver positive input pin e2 rvinn i receiver negative input pin b4 rin3/in3+ i analog input pin b5 lin3/in3- i analog input pin c5 vcom o analog common voltage output pin c4 rin2/in2+ i analog input pin d3 lin2/in2- i analog input pin d5 rin1/in1+ i analog input pin f5 lin1/in1- i analog input pin e5 svdd - speaker-amp power supply pin e4 vss2 - speaker-amp ground pin (ground 2 pin) f4 spp o positive speaker-amp output pin d4 spn o negative speaker-amp output pin f1 mixo o mix-amp output pin f3 spin i speaker-amp input pin note 1. do not allow all input pins except analog input pins (lin1/in1-, rin1/in1+, lin2/in2-, rin2/in2+, lin3/in3-, rin3/in3+, spin, rvinp and rvinn) to float. handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog hpl, hpr, mixo, spin, spp, spn, lin1/in1-, rin1/in1+, lin2/in2-, rin2/in2+, lin3/in3-, rin3/in3+, rvinp, rvinn, test these pins must be open. [ak4213] ms0949-e-01 - 5 - 2008/07 absolute maximum rating (vss1=vss2=vss2=0v; note 2 ) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v ( note 3 ) digital i/f tvdd ? 0.3 6.0 v speaker-amp & headphone-amp svdd ? 0.3 6.0 v charge pump pvdd ? 0.3 4.0 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 4 ) vina1 ? 0.3 (avdd + 0.3) or 6.0 v ( note 5 ) vina2 ? 0.3 (svdd + 0.3) or 6.0 v digital input voltage ( note 6 ) vind ? 0.3 (tvdd + 0.3) or 6.0 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c ta=85oc ( note 8 ) pd1 - 0.65 w maximum power dissipation ( note 7) ta=70oc ( note 9 ) pd2 - 0.8 w note 2. all voltages with respect to ground. note 3. vss1, vss2, and vss3 must be connected to the same analog plane. note 4. lin1/in1-, rin1/in1+, lin2/in2-, ri n2/in2+, lin3/in3-, rin3/in3+ and spin pins the maximum value is low value either (avdd+0.3)v or 6.0v. note 5. rvinp and rvinn pins the maximum value is low value either (svdd+0.3)v or 6.0v. note 6. sda, scl and pdn pins. the maximum value is low value either (tvdd+0.3)v or 6.0v. pull-up resistors at scl and sda pins should be connected to (tvdd + 0.3)v or less voltage. note 7. in case that pcb wiring density is 300% or more. this power is the ak4213 internal dissipation that does not include power of externally connected headphone and speaker. note 8. in the case of ta=85oc, hp-amp and spk-amp must not be powered-up simultaneously. when spk-amp be used, hp-amp should power-down, and the power of spk-amp should less than 1.3w @8 ? . note 9. in the case of ta=70oc, hp-amp and spk-amp can be powered-up simultaneously. when hp-amp and spk-amp be used simultaneously, the power of hp-amp should less than 30mw @16 ? , and the power of spk-amp should less than 1.2w @8 ? . warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. [ak4213] ms0949-e-01 - 6 - 2008/07 recommend operating conditions (vss1=vss2=vss3=0v; note 2) parameter symbol min typ max units power analog avdd 2.7 3.3 3.6 v supplies digital i/f tvdd 1.6 1.8 3.6 v ( note 10 ) speaker-amp & headphone-amp svdd 3.0 3.6 5.5 v charge pump pvdd 2.7 3.3 3.6 v difference avdd - pvdd -0.3 0 0.3 v svdd - avdd -0.3 - - v note 10. the power up sequence among avdd, tvdd, svdd, and pvdd is not critical. the pdn pin must be held to ?l? when power-up. the pdn pin must be set to ?h? after power supplies are powered-up. the ak4213 should be operated by the recommended power-up/down sequence shown in ?system design? to avoid pop noise at speaker output and headphone output. the ak4213 supports the following two cases of partial power on/off. in these cases, the pdn pin must be ?l?. 1. tvdd=svdd=on: avdd=pvdd can be power on/off. 2. tvdd=on: avdd=pvdd=svdd can be power on/off. when the power state is changed from off to on in the above cases, the pdn pin must be changed from ?l? to ?h? after all power supply pins are supplied. ?l? time of 150ns or more is needed to reset the ak4213. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. [ak4213] ms0949-e-01 - 7 - 2008/07 analog characteristics (ta=25 c; avdd=pvdd=3.3v, svdd=3.6v, tvdd=1.8v, vss1 =vss2=vss3=0v; input signal frequency =1 khz; measurement band width=10hz 20khz; headphone-amp: r l =16 ; speaker-amp: r l =8 + 10 h; charge pump circuit external capacitance: c1=c2= 2.2 f ( figure 4 ); unless otherwise specified) parameter min typ max units lin1, rin1, lin2, rin2, lin3, rin3 pins input resistance 25 50 110 k input analog volume: l1v3-0, r1v3-0, l2v3-0, r2v3-0, l3v3-0, r3v3-0 bits step size 1 2 3 db gain control range -20 - +10 db mix-amp: mixo pin load resistance 10 - - k load capacitance - - 30 pf headphone-amp: lin/rin ? hpl/hpr pins, hpga = 0db output power (thd+n=1%) svdd=3.3v - 64 - mw thd+n: 0.7vrms single-ended input, po = 30mw - -58 -40 db output noise level (a-weighted) ( note 11 ) - 24 40 vrms interchannel gain mismatch - 0.2 0.8 db load resistance 16 - - load capacitance - - 300 pf output voltage: 0.7vrms single-ended input 0.62 0.69 0.76 vrms psrr 217hz ( note 12 ) 1khz ( note 12 ) 217hz ( note 13 ) 1khz ( note 13 ) - - - - 70 70 100 80 - - - - db db db db interchannel isolation 60 80 - db headphone analog volume (hpga4-0 bits) step size 0.5 2 3.5 db gain control range -50 - +12 db class-d speaker-amp: lin or rin ? spp/spn; btl, alc = off, input volume=spga=0db, alc off output power (thd+n=10%) svdd=5.0v svdd=3.6v - - 1.6 0.8 - - w w output level svdd=5.0v, input level = 0.85vrms ( note 14 ) svdd=3.6v, input level = 0.64vrms ( note 15 ) svdd=3.6v, input level = 0.46vrms ( note 16 ) - - 1.33 2.7 2.0 1.48 - - 1.63 vrms vrms vrms thd+n: po=0.25w, input level =0.46vrms ( note 16 ) - -65 -40 db output noise level (a-weighted) ( note 17 ) - 85 150 vrms load resistance 8 - - load capacitance ( note 21 ) - - 300 pf psrr 217hz ( note 18 ) 1khz ( note 18 ) 217hz ( note 19 ) 1khz ( note 19 ) - - - - 60 50 50 50 - - - - db db db db switching frequency 150 250 400 khz current limit at short ( note 20 ) - 40 120 ma start-up time 18 30 48 ms [ak4213] ms0949-e-01 - 8 - 2008/07 parameter min typ max units spin pins input resistance 15 26 36 k speaker analog volume: spga5-0 bits step size 0.1 0.5 0.9 db gain control range -12 - +19.5 db bypass mode: figure 2 , input level = 1.13vrms, common voltage = 1.8v, measured by spp/spn pins 1.13vrms, 3.2vpp - -50 - db thd+n 0.71vrms, 2.0vpp - -60 -50 db output level - 0.46 - vrms switch on resistance (bype bit = ?1?) - 2.8 - switch off isolation ; 3.6v dc input, figure 3 (spp/spn pins? rvinp/rvinn pins) - 90 - db power supplies power supply current normal operation (pdn pin = ?h?) avdd+tvdd: all on ( note 22 ) - 4.0 6.5 ma hp-amp on ( note 23 ) - 2.0 - ma spk-amp on ( note 24 ) - 2.8 - ma pvdd (no output): hp-amp on - 1.3 3.2 ma svdd (no output): hp-amp on - 2.0 4.0 ma spk-amp on 1.0 4.0 ma power-down mode (pdn pin = ?l?) ( note 25 ) avdd+pvdd+svdd+tvdd - 1 30 a note 11. in case of singled-ended mode. only mixer path of inputting signal is on. (in case of differential mode, this value is typically 29 vrms.) note 12. psr is applied to avdd and pvdd with 100mpvpp sine wave. note 13. psr is applied to svdd with 0.89vpp sine wave. note 14. in case of single-ended mode. (in case of differentia l mode, the input signal level is 0.425vrms. the signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) note 15. in case of single-ended mode. (in case of differentia l mode, the input signal level is 0.32vrms. the signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) note 16. in case of single-ended mode. (in case of differentia l mode, the input signal level is 0.23vrms. the signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) note 17. in case of singled-ended mode. only mixer path of inputting signal is on. (in case of differential mode, this value is typically 90 vrms. ) note 18. psr is applied to avdd with 100mpvpp sine wave. note 19. psr is applied to svdd with 100mpvpp sine wave. note 20. average current between svdd and vss2 when th e spp and spn pins are shorted and 0.85vrms, 1khz sine wave is input to the ak4213 in single-ended mode. note 21. this is capacitance value between output pin and vss1. when a capacitor is connected between output pins, load capacitance for each output pin doubles. therefore, it is necessary to deci de load capacitance in consideration of these. note 22. all circuits are powered-up. (pmvcm = pmosc = pmcp = pmhpl = pmhpr = pmmhl = pmmhr = pmspk = pmmsp = pmv1 = pmv2 = pmv3 bits= ?1?) note 23. minimum blocks for headphone-amp path are powered-up. (pmvcm = pmosc = pmcp = pmhpl = pmhp r = pmmhl = pmmhr = pmv1 bits= ?1?, pmspk = pmmsp = pmv2 = pmv3 bits= ?0?) note 24. minimum blocks for speaker-amp path are powered-up (pmvcm = pmosc = pmcp = pmspk = pmmsp = pmv1 bits= ?1?, pmhpl = pmhpr = pmmhl = pmmhr = pmv2 = pmv3 bits= ?0?) note 25. all digital input pins are held at vss1. [ak4213] ms0949-e-01 - 9 - 2008/07 spp pin a k4213 spn pin a lc spk-amp receiver-amp rvinp pin rvinn pin sw1 sw2 3.9 3.9 8 input voltage: 1.13vrms, common voltage=1.8v measurement point of thd+n and output voltage figure 2. connection with external rcv-amp spp pin a k4213 spn pin a lc spk-amp rvinp pin rvinn pin sw1 sw2 50 dc input voltage: 3.6v measurement point of switch off isolation 50 dc input voltage: 3.6v spp pin a k4213 spn pin a lc spk-amp rvinp pin rvinn pin sw1 sw2 50 dc input voltage: 3.6v measurement point of switch off isolation 50 dc input voltage: 3.6v figure 3. measurement circuit of switch off isolation pvee pin charge pump circuit cn pin c2 cp pin headphone-amp negative voltage c1 vss3 figure 4. charge pump circuit external capacitor [ak4213] ms0949-e-01 - 10 - 2008/07 dc characteristics (ta= -40~85 c; avdd=pvdd=2.6 3.6v; svdd=2.6 5.5v; tvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage (2.2v tvdd 3.6v) vih 70 % tvdd - - v (1.6v tvdd < 2.2v) vih 80%tvdd - - v low-level input voltage (2.2v tvdd 3.6v) vil - - 30 % tvdd v (1.6v tvdd < 2.2v) vil - - 20 % tvdd v low-level output voltage (2.0v tvdd 3.6v: iout = 3ma) vol - - 0.4 v (1.6v tvdd < 2.0v: iout = 3ma) vol - - 20%tvdd v input leakage current iin - - 2 a switching characteristics (ta= -40~85 c; avdd=pvdd =2.6 3.6v; svdd=2.6 5.5v; tvdd=1.6 3.6v) parameter symbol min typ max units control interface timing: ( note 26 ) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 27 ) thd:dat 0 - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 28 ) tpd 150 - - ns note 26. i 2 c is a registered trademark of philips semiconductors. note 27. data must be held long enough to bridge the 300ns-transition time of scl. note 28. the pdn pin must change from ?l? to ?h? after all power supply pins are supplied. the ak4213 can be also reset by bringing the pdn pin = ?l? to ?h?. [ak4213] ms0949-e-01 - 11 - 2008/07 timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 5. i 2 c bus mode timing tpd vil pdn figure 6. power-down & reset timing [ak4213] ms0949-e-01 - 12 - 2008/07 operation overview input selector & volume the ak4213 has two input modes that are singled-ended and diffe rential. single-end and differential modes are selected by sd3-1 bits. in the differential mode, the input path and volume are controlled via the left channel registers, and the right channel registers are ignored. the ak4213 has three mi xing circuits that used for l/r channels of headphone amplifier and speaker amplifer . the each mixing circuit can be controlled i ndependently. when all input paths are off, the mixing circuit outputs common voltage . the input volume can control each i nput path independe ntly. the input volume ranges from +10 db to ?20db in 2db step. when changing the input volume, pop noise may occur. each input volume has power management mode which is common to th e left and right channels. the power-up/down of input volume can be controlled by pmv3-1 bits. the power-up time is 16.4ms(typ.) and 26.3ms(max). ac coupling capacitor of 0.22 f or less should be connected to linx/rinx (x=1~3) pins to reduce the pop noise at the power-up of the input volume block. l1v3-0 bit r1v3-0 bit l2v3-0 bit r2v3-0 bit l3v3-0 bit r3v3-0 bit gain (db) step fh +10 eh +8 : : ch +4 bh +2 ah 0 (default) 9h ? 2 8h ? 4 : : 2h ? 16 1h ? 18 0h ? 20 2db table 1. input volume setting sd3 bit sd2 bit sd1 bit input mode 0 single-ended mode (default) 1 differential mode table 2. input mode setting [ak4213] ms0949-e-01 - 13 - 2008/07 lin1/in1 ? prel to mixo pin spkl1 bit spkr1 bit spkl2 bit spkr2 bit spkl3 bit spkr3 bit mixing & selector vol ( l1v3-0 bits ) rin1/in1+ lin2/in2- rin2/in2+ lin3/in3- rin3/in3+ vol ( r1v3-0 bits ) vol ( l2v3-0 bits ) vol ( r2v3-0 bits ) vol ( l3v3-0 bits ) vol ( r3v3-0 bits ) prel to lch headphone-amp hpll1 bit hplr1 bit hpll2 bit hplr2 bit hpll3 bit hplr3 bit mixing & selector prel to rch headphone-amp hprl1 bit hprr1 bit hprl2 bit hprr2 bit hprl3 bit hprr3 bit mixing & selector figure 7. input selector & volume in single-ended mode (sd3-1 bits = ?000?) [ak4213] ms0949-e-01 - 14 - 2008/07 in1 ? prel to mixo pin spkl1 bit spkl2 bit spkl3 bit mixing & selector vol ( l1v3-0 bits ) in1+ in2 ? in2+ in3 ? in3+ vol ( l2v3-0 bits ) vol ( l3v3-0 bits ) prel to lch headphone-amp hpll1 bit hpll2 bit hpll3 bit mixing & selector prel to rch headphone-amp hprl1 bit hprl2 bit hprl3 bit mixing & selector figure 8. input selector and volume in differential mode (sd3-1 bits = ?111?) [ak4213] ms0949-e-01 - 15 - 2008/07 class-d speaker-amp the output signal from alc block is conve rted by pwm and is outputted from the spp/spn pins by btl. the signal of alc block is inputted from the spin pin. the bpf (band pass filter) is made by inserting the capacitor and resistor between the mixo pin and the spin pin. a 0.1uf capacitor must be connected between the mixo pin and the spin pin in order to cancel dc offset of mixing & se lector circuit, if the bpf is not needed. 1k 0.033 f mixo pin typ.26k - + a lc 0.015 f ak4213 spin pin spga5-0bits mixing & selector figure 9. example of band-pass-filter for sp eaker (bpf = typ. 442hz to 4.83khz @ -3db) mixo pin typ.26k - + a lc 0.1 f ak4213 spin pin spga5-0bits mixing & selector figure 10. example of normal connection for speaker (fc = typ. 66hz @ -3db) when the input signal level is 0.7vrms in single-ended mode, the speaker-amp outputs 0.6w at alc=off and spga=0db. when the stereo signal is input to the ak4213 in single-ended mode, the input volume of left and right channels should be set to ?-6db? and left and speaker mixer path of left and right channels should be on. in this case, the speaker outputs the signal level of ?(l +r)/2?. the default internal gain is +9.82db.when alc is on (alc bit = ?1?), alc output level is automatically adjusted to ? 7.5dbv ? 9.5dbv at lmth bit = ?0? and ? 11.5dbv ? 13.5dbv at lmth bit = ?1?. the reference level is set by ref5-0 bits. the internal gain of class-d spk-amp is fixed to +11.76db input volume (-1.94db @ vol=0db) mixing & selector (0db) alc off: spga5-0 bits alc on: ref5-0 bits class-d (+11.76db) input figure 11. speaker-amp path level diagram [ak4213] ms0949-e-01 - 16 - 2008/07 when pmspk bit is set to ?0?, th e speaker block (alc + speaker-amp) can be powered-down completely. the power-up / down transition time is 30ms (typ.) and 48ms (max). the write operation to spga5-0 bits is prohibited within 1.6ms after pmspk bit is set to ?1?. pmspk bits speaker-amp 0 power-down (default) 1 power-up & output table 3. speaker-amp output state bypass mode when bype bit is ?1? (sw1=sw2=on), input signals to the rvinp pin and the rvinn pin are output from the spp pin and the spn pin respectively. then spk-amp is in hi-z. when bype bit is ?0? (sw1=sw2=off), the signal of spk-amp are output from the spp/spn pin. in case of pmspk bit = ?1?, bype bit is ignored. bypass mode can be on when all power management register are ?0? setting including vcom and inter-oscilloscope. in case of bypass mode setting, pmvcm bit should be set to ?1? if thermal shut-down function is used. pmspk bit bype bit mode 0 0 power-down (spp/spn pins are hi-z) 0 1 bypass mode 1 x speaker mode table 4. speaker and receiver modes (x: don?t care) spp pin a k4213 spn pin a lc spk-amp receiver-amp rvinp pin rvinn pin sw1 sw2 3.9 3.9 speaker figure 12. bypass mode [ak4213] ms0949-e-01 - 17 - 2008/07 alc operation the alc (automatic level control) operation of speaker-amp output is operated by alc block when alc bit = ?1?. when alc bit is ?0?, the speaker volume depends on the setting value of spga5-0 bits. (1) alc limiter operation during the alc limiter operation, when alc output level exceeds the alc limiter detection level (lmth bit), the spga value is attenuated automatically to the amount defined by alc limiter att step (lmth1-0 bits). when zelmn bit is set to ?0? (zero crossing detection is enabled), the spga value is changed by the alc limiter operation at the zero crossing point or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout periods of both the alc limiter and recovery operation. when zelmn bit = ?1? (zero crossing detection is disa bled), spga value is imme diately (period: typ. 125 s, max. 200 s) changed by alc limiter operation. attenuation step is fi xed to 1 step regardless of the setting of lmat1-0 bits. the attenuate operation is executed continuously until the alc output level becomes alc limiter detection level or less. after completing the attenuate operation, unless alc bit is ch anged to ?0?, the operation repeats when the input signal level exceeds lmth bit. lmth bit alc limiter detection level alc recovery waiting counter reset level 0 alc output -7.5dbv ? 7.5dbv > alc output ? 9.5dbv (default) 1 alc output -11.5dbv ? 11.5dbv > alc output ? 13.5dbv note: alc limiter detection level and alc rec overy waiting counter re set level do not depend on operation voltage. table 5. alc limiter detection level / recovery counter reset level zelmn bit lmat1 lmat0 alc limiter att step 0 0 1 step 0.5db (default) 0 1 2 step 1.0db 1 0 4 step 2.0db 0 1 1 8 step 4.0db 1 x x 1step 0.5db table 6. alc limiter att step (x: don?t care) zero crossing timeout ztm1 bit ztm0 bit typ. max 0 0 16.4ms 26.3ms 0 1 32.8ms 51.5ms (default) 1 0 65.6ms 105.0ms 1 1 131.2ms 210.0ms table 7. alc zero crossing timeout period [ak4213] ms0949-e-01 - 18 - 2008/07 (2) alc recovery operation the alc recovery operation waits for the wtm2-0 bits to be set after completing the alc limiter operation. if the input signal does not exceed ?alc recovery wa iting counter reset level? during wait time, the alc recovery operation is executed. the spga value is automatically incremented by rgain1-0 bits up to the set reference level (ref5-0 bits) with zero crossing detection which timeout period is set by ztm1-0 bits. the alc recovery operation period is set by wtm2-0 bits. when zero cross is detect ed during the wait period set by wtm2-0 bits, the alc recovery operation waits until wtm2-0 period and the next recovery operation is executed. the setting period of wtm2-0 bits should be same as ztm1-0 bits or longer period. when rgain 1-0 bits are set to ?10?, the alc reco very operation is not executed even the alc limiter operation is executed. during the alc recovery operation, wh en the alc output level exceeds alc lim iter detection level (lmth bit), the alc limiter operation is executed immediately. when ?alc recovery waiting counter reset level alc output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level > alc output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when larg e noise is input to microphone instantaneously, the quality of small singal level in the large noise can be improved by this fast recovery operation. recovery waiting timer wtm2 bit wtm1 bit wtm0 bit typ. max 0 0 0 16.4ms 26.3ms 0 0 1 32.8ms 51.5ms 0 1 0 65.6ms 105.0ms 0 1 1 131.2ms 210.0ms 1 0 0 262.4ms 419.9ms 1 0 1 524.8ms 839.7ms (default) 1 1 0 1049.6ms 1679.4ms 1 1 1 2099.2ms 3358.8ms table 8. alc recovery waiting timer period rgain1 rgain0 gain step 0 0 1 step 0.5db (default) 0 1 2 step 1.0db 1 0 0 step 0db (only limiter operation) 1 1 reserved table 9. alc recovery gain step ref5-0 gain (db) step 3fh +19.5 3eh +19.0 3dh +18.5 3ch +18.0 (default) : : 19h +0.5 18h 0.0 17h ? 0.5 : : 02h ? 11.0 01h ? 11.5 00h ? 12.0 0.5db table 10. reference level at alc recovery operation [ak4213] ms0949-e-01 - 19 - 2008/07 (3) example of alc operation table 11 shows the example of the alc setting. the alc starts from the value of spga5-0 bits. register name comment data parameter lmth limiter detection level 0 ? 7.5dbv zelmn limiter zero crossing enable 0 limiter zero crossing enable wtm2-0 recovery waiting period 101 typ. 524.8ms ref5-0 maximum gain at recovery operation 3ch +18db lmat1-0 limiter att step 00 0.5db rgain1-0 recovery gain step 00 0.5db ztm1-0 zero-crossing timeout 01 typ. 32.8ms alc alc enable bit 1 enable table 11. example of the alc setting the following registers should not be changed during the al c operation. these bits should be changed after the alc operation is finished by alc bit = ?0?. - lmth, lmat1-0, wtm2-0, rgain1-0, ref5-0, ztm1-0 and zelmn bits alc=off wr (spga5-0) wr (ztm1-0, wtm2-0) alc operation example: limiter: zero crossing enable recovery cycle = typ. 524.8ms limiter and recovery step = 1 maximum gain = +18db limiter detection level = ? 7.5dbv alc bit = ?1? (1) addr=0eh, data=3ch (3) addr=10h, data=0dh wr (ref5-0) (2) addr=0fh, data=3ch wr (zelmn, lmat1-0, rg ain1-0, lmth, alc=?1?) (4) addr =11h, data=40h * the value of spga should be the same or smaller than ref?s. note: wr: write figure 13. registers set-up sequence at alc operation [ak4213] ms0949-e-01 - 20 - 2008/07 speaker volume (spga: manual mode) the speaker volume becomes manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. set-up the registers for the alc operation (ztm1-0, lmth and etc). 2. set-up the initial value of spga when alc starts. 3. when spga is used as a manual volume. spga5-0 bits set the gain of the volume control. the spga value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. when pmspk bit is ?0?, spga5-0 bits does not write to anything. after pmspk bit is changed from ?0? to ?1?, writing to spga5-0 bits is inhibit within 1.6ms. when changing from pmspk bit = ?0? to pmspk bit = ?1?, spga volume becomes default value (0db) regardless of the setting of spga5-0 bits. spga5-0 bits gain (db) step 3fh +19.5 3eh +19.0 3dh +18.5 3ch +18.0 : : 19h +0.5 18h 0.0 (default) 17h ? 0.5 : : 02h ? 11.0 01h ? 11.5 00h ? 12.0 0.5db table 12. speaker-amp volume setting when writing to the spga5-0 bits conti nuously, the control register should be written with an interval more than zero crossing timeout. a lc bit a lc status disable enable disable spga5-0 bits 3ch(+18db) internal spga 3ch(+18db) 3ch(+18db) --> 19h(+0.5db) 3ch(+18db) (1) (2) figure 14. spga value during alc operation (1) alc operation starts from the spga value when alc bit is changed to ?1?. (2) writing to spga registers is ignored during alc operation. after alc is disabled, the spga changes to the last written data by twice period of zero cro ssing or timeout. when alc is enabled ag ain, alc bit should be set to ?1? in an interval more than zero crossing timeout period after alc bit = ?0?. [ak4213] ms0949-e-01 - 21 - 2008/07 charge pump circuit the internal charge pump circuit generates negative volta ge(pvee) from pvdd voltage for headphone amplifiers. when pmcp bit is set to ?1?, the charge pump circuit is pow ered-up. then pmosc and pmvcm must be set to ?1?. the power up time of charge pump circuit is typically 6.2ms and maximum 10ms.when pmhpl bit = ?1? or pmhpr bit = ?1?, the headphone-amp is powered-up after the charge pump circuit is powered-up ( figure 17 ). headphone-amp (hpl/hpr pins) power supply voltage for headphone amplifiers is applie d from a regulator for positive power and charge-pump for negative power. regulator is driven by svdd and charge- pump is driven by pvdd. the pvee pin outputs the negative voltage generated by the internal charge pump circuit. the headphone amplifier output is single-ended and centered on 0v (vss3). therefore, the capacito r for ac-coupling can be removed. the minimum load resistance is 16 . when the input signal level is 0.7vrms at single-ended mode, the output voltage is 0.69vrms (= 30mw @ 16 ) at hpg43-0 bits = ?19h? (0db). the output level of hea dphone-amp can be controlled by hpga4-0 bits. this volume setting is common to l/r channels and can attenuate / gain the mixer output from +12db to ?50db in 2db step. hpga4-0 bits gain (db) step 1fh +12 1eh +10 : - 1ah +2 19h 0 (default) 18h ? 2 17h ? 4 16h ? 6 : : 2h ? 46 1h ? 48 0h ? 50 2db table 13. headphone-amp volume setting input volume (-1.94db @ vol =0db) mixing & selector (0db) hp volume (hpga=0db) hp-amp (+1.94db) input figure 15. headphone-amp path level diagram [ak4213] ms0949-e-01 - 22 - 2008/07 the headphone output is enabled when hpmtn bit is ?1? and muted when hpmtn bit is ?0?. the mute on/off time is set by pts1-0 bits when moff bit is ?0?. when moff bit is ?1?, the mute on/off is switched immediately. when pmhpl and pmhpr bits are ?0?, the headphone-amps are powered-down completely. at that time, the hpl and hpr pins go to vss3 voltage via the internal pulled-down resistor. the pulled-down resistor is 20 (typ) at hpz bit = ?0?, 25k (typ) at hpz bit = ?1?. the power-up time is 16.4ms (typ.) and 26.3ms (max.), and power up/down is executed immediately. pmcp/pmvcm pmhpl/r hpmtn hpz mode hpl/r pins x 0 x 0 power-down & mute pulled-down by 20 (typ) (default) x 0 x 1 power-down pulled-down by 25k (typ) 1 1 0 0 mute vss3 1 1 1 0 normal operation normal operation table 14. headphone amplifier mode setting (x: don?t? care) [ak4213] ms0949-e-01 - 23 - 2008/07 transition time the mute on/off time of headphone-amp is set to pts1 -0 bits. these operations are soft transition. the enable/disable for the soft transition is set by moff bit. the soft transition is disabled while moff bit is ?1?, the mute on/off is switched immediately. as shown in table 15 , if the soft transition is enabled, the register value of the same address must be changed in an interval more than transition time. the write operation is ignored if the sa me values are written as the previous write operation. address register name enable / disable pts1-0 bits 0dh hpmtn bit moff bit table 15. registers with transition time mute on/off time pts1 pts0 typ. max. 0 0 16.4ms 26.3ms (default) 0 1 32.8ms 51.5ms 1 0 65.6ms 105.0ms 1 1 131.2ms 210.0ms table 16. headphone-amp mute on/off transition time thermal shutdown function when the internal device temperature rise s up irregularly (e.g. output pins of speaker amplifier are shortened.), the charge pump, headphone amplifier, and speaker amplifier ar e automatically powered-down and then thdet bit becomes ?1?. the powered-down charge pump circuit, headphone amplifier and speaker amplifier do not return to normal operation unless hp/spk-amp blocks of the ak4213 are reset by the pdn pin ?l?. the device status can be monitored by thdet bit. [ak4213] ms0949-e-01 - 24 - 2008/07 power-up/down sequence 1) hp-amp power supply pdn pin pmvcm bit pmosc bit pmmhl/r bit pvee pin hpl/hpr pins (3) pmcp bit (1) (9) pmhpl/r bit (2) (7) (10) hpmtn bits 0v pvee 0v normal mute mute (8) (4) 0v 0v pmvx bits (6) input volume output state hi-z vcom hi-z (5) 0s figure 17. hp-amp power-up/down sequence example (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4213. the power must be on in the state of the pdn pin = ?l?. the pdn pin must be set to ?h? after power supply (avdd, tvdd, pvdd, svdd) on. (2) pts1-0, moff, hpga4-0, and sd3-1 bits must be set during this period. (3) regulator, power-up of charge pump, internal oscilla tor, vcom, and hp-amp mixer & selector: pmcp = pmmhl = pmmhr = pmosc = pmvcm bits = ?0? ? ?1? the pvee pin becomes pvee voltage within 10ms (max.). (4) power-up of input volume: pmvx bit = ?0? ? ?1? input volume setting (l1v3-0, l2v3-0, l3v3-0, r1v3-0, r2v3-0, r3v3-0 bits) input path setting (hpll3-1, hplr3-1, hprr3-1, hprl3-1 bits) input volume block is powered-up within 26.3ms (max.). input path and volume can be set when input volume block is powered-up. (5) if pmcp and pmhpl/r bits are set to ?1? at the same tim e or pmhpl/r bits are set to ?1? during the power-up time of the charge pump circuit, headphone-amp is powered-up after the charge pump circuit is powered-up. (6) power-up of headphone-amp: pmhpl/r bits = ?0? ? ?1? headphone-amp is in the mute state and becomes ground level. headphone-amp power-up time is 26.3ms (max.). (7) headphone-amp mute release: hpmtn bit = ?0? ? ?1? headphone-amp goes to the normal operation after the transition time. headphone-amp mute release time depends on the setting of pts1-0 and moff bits. (8) headphone-amp mute: hpmtn bit = ?1? ? ?0? headphone-amp goes to the mute state after the transition time set by pts1-0 and moff bits. (9) headphone-amp power-down: pmhpl/r bits = ?1? ? ?0? headphone-amp is powered-down immediately. (10) power-down of charge pump, internal oscillator, vcom, and hp-amp mixer & selector: pmcp = pmmhl = pmmhr = pmosc = pmvcm bits = ?1? ? ?0? the pvee pin becomes 0v according to th e time constant of the capacitor at th e pvee pin and the internal resistor. the internal resistor is 17.5k (typ.). charge pump circuit can be powered-up during this period. [ak4213] ms0949-e-01 - 25 - 2008/07 2) spk-amp power supply pdn pin pmvcm bit pmosc bit clock input spp/spn pins pmmsp bit pmspk bit (1) (2) hi-z normal (3) hi-z pmvx bits don?t care don?t care input volume output state hi-z vcom hi-z 0s (4) 0s spga bits (5) 1.6ms (7) hi-z (7) (8) 500us normal default xxh xxh default (5) 1.6ms default a lc state disable enable disable (6) disable (6) enable a lc bit figure 18. spk-amp power-up/down sequence example (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4213. the power must be on in the state of pdn pin = ?l?. the pdn pin must be set to ?h? after power supply (avdd, tvdd, pvdd, svdd) are on. (2) power-up of vcom and the internal oscillator: pmvcm= pmosc: ?0? ? ?1? sd3-1 bits must be set during this period. (3) power-up of input volume: pmvx bit = ?0? ? ?1? input volume setting (l1v3-0, l2v3-0, l3 v3-0, r1v3-0, r2v3-0, r3v3-0 bits) input path setting (spkl3-1, spkr3-1 bits) input volume block is powered-up within 26.3ms (max.). input path and volume can be set when input volume block is powered-up. (4) power-up of spk-amp and spk-amp mixer & selector: pmmsp = pmspk bits =?0? ? ?1? (5) spga5-0 bits setting: the setting of spkg5-0 and alc bits is enabled at 1.6ms or more after pmspk bit is set to ?1?. (6) alc setting: alc is enabled at 30ms (max.). refer to ?registers set-up sequence at alc operation?. (7) speaker-amp goes to the normal operation at 48ms (max.) after pmspk bit is changed to ?1?. (8) once speaker-amp is powered-down, speak er-amp can be powered-up again at 500 s or more lately. when pmmsp, pmspk bit = ?1? ? ?0?, before pmvcm,pmosc bit = ?1? ? ?0?, please wait more than 0.5ms. [ak4213] ms0949-e-01 - 26 - 2008/07 3) change of the signal path to hp-amp or spk-amp example: the signal path changes from lin1/rin1 to lin2/rin2 when hp-amp is powered-up. (4) pmv2 bit hi-z output 0s pmv1 bit lin1/rin1 volume output state output hi-z hpll1/r1 bits hpll2/r2 bits vcom 0s lin2/rin2 volume output state (1) (5) (2) (3) figure 19. example of changing signal path during hp-amp is powered-up (1) signal path off from lin1/rin1 to hp-amp: hpll1 = hplr1 bits = ?1? ? ?0? (2) input volume of lin1/rin1 is powered-down: pmv1 bit = ?1? ? ?0? (3) input volume of lin2/rin2 is powered-up: pmv2 bit = ?0? ? ?1? (4) input volume of lin2/rin2 is powered-up at 26.3ms (max.). (5) signal path on from lin2/rin2 to hp-amp: hpll2 = hplr2 bits = ?0? ? ?1? [ak4213] ms0949-e-01 - 27 - 2008/07 serial control interface the ak4213 supports a fast-mode i 2 c-bus system (max: 400khz). pull-up resistors at the scl and sda pins should be connected to (tvdd + 0.3)v or less voltage. 1. write operations figure 20 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 26 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010011?( figure 21 ). if the slave address matches that of the ak4213, the ak4213 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 27 ). an r/w bit value of ?1? indicates that the r ead operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4213. the format is msb first, and those most significant 3-bit are fixed to zero ( figure 22 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 23). the ak4213 generates an acknowledge after each byte is received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 26 ). the ak4213 can perform more than one by te write operation per sequence. after receipt of the third byte the ak4213 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 5-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 12h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 28) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 20. data transfer sequence 0 0 1 0 0 1 1 r/w figure 21. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 22. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 23. byte structure after the second byte [ak4213] ms0949-e-01 - 28 - 2008/07 2. read operations set the r/w bit = ?1? for the read operation of the ak4213. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the internal 5-bit address counter is incremented, a nd the next data is automatically taken into the next address. if the address ex ceeds 12h prior to generating stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4213 supports two basic read operations: current address read and random address read. 2-1. current address read the ak4213 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit ?1?, the ak4213 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknow ledge but generates stop condition, the ak4213 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 24. current address read 2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave addr ess with the r/w bit ?1?. the ak4213 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge to the data but generates a st op condition, the ak4213 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 25. random address read [ak4213] ms0949-e-01 - 29 - 2008/07 scl sda stop condition start condition s p figure 26. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 27. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 28. bit transfer on the i 2 c-bus [ak4213] ms0949-e-01 - 30 - 2008/07 register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 pmmhr pmmhl pmhpr pmhpl pmcp pmosc pmvcm 01h power management 1 0 0 0 0 0 pmmsp 0 pmspk 02h power management 2 0 0 0 0 0 pmv3 pmv2 pmv1 03h mode control 0 thdet 0 0 bype 0 sd3 sd2 sd1 04h lch headphone mixer 0 0 hplr3 hpll3 hplr2 hpll2 hplr1 hpll1 05h rch headphone mixer 0 0 hprr3 hprl3 hprr2 hprl2 hprr1 hprl1 06h speaker mixer 0 0 spkr3 spkl3 spkr2 spkl2 spkr1 spkl1 07h reserved 0 0 0 0 0 0 0 0 08h input volume #1 r1v3 r1v2 r1v1 r1v0 l1v3 l1v2 l1v1 l1v0 09h input volume #2 r2v3 r2v2 r2v1 r2v0 l2v3 l2v2 l2v1 l2v0 0ah input volume #3 r3v3 r3v2 r3v1 r3v0 l3v3 l3v2 l3v1 l3v0 0bh reserved 0 0 0 0 0 0 0 0 0ch mode control 1 0 0 moff 0 pts1 pts0 0 0 0dh headphone pga control 0 hpz hpmtn hpga4 hpga3 hpga2 hpga1 hpga0 0eh speaker pga control 0 0 spga5 spga4 spga3 spga2 spga1 spga0 0fh alc mode control 1 0 0 ref5 ref4 ref3 ref2 ref1 ref0 10h alc mode control 2 0 0 0 ztm1 ztm0 wtm2 wmt1 wmt0 11h alc mode control 3 0 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth 12h test 0 0 0 0 0 0 0 0 all registers writing are i nhibited at pdn pin = ?l?. the pdn pin = ?l? resets the registers to their default value. note 29. the bit indicated as ?0? in the register map must contain a ?0? value. note 30. only write to address 00h to 12h. [ak4213] ms0949-e-01 - 31 - 2008/07 register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 pmmhr pmmhl pmhpr pmhpl pmcp pmosc pmvcm r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmvcm: power management for vcom and regulator which used for headphone-amp 0: power off (default) 1: power on pmosc: power management for internal oscillator 0: power off (default) 1: power on pmcp: power management for charge pump circuit 0: power off (default) 1: power on pmhpl: power management for lch headphone-amp 0: power off (default) 1: power on pmhpr: power management for rch headphone-amp 0: power off (default) 1: power on pmmhl: power management for mixing & selector circuit of lch headphone-amp 0: power off (default) 1: power on pmmhr: power management for mixing & selector circuit of rch headphone-amp 0: power off (default) 1: power on [ak4213] ms0949-e-01 - 32 - 2008/07 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 1 0 0 0 0 0 pmmsp 0 pmspk r/w rd rd rd rd rd r/w rd r/w default 0 0 0 0 0 0 0 0 pmspk: power management for speaker-amp 0: power off (default) 1: power on when pmspk bit is ?0?, spp pin and spn pin becomes hi-z. pmmsp: power management for mixing & selector circuit of speaker-amp 0: power off (default) 1: power on addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h power management 2 0 0 0 0 0 pmv3 pmv2 pmv1 r/w rd rd rd rd rd r/w r/w r/w default 0 0 0 0 0 0 0 0 pmv1: power management for input volume #1 0: power off (default) 1: power on pmv2: power management for input volume #2 0: power off (default) 1: power on pmv3: power management for input volume #3 0: power off (default) 1: power on all blocks can be powered-down by setting the pdn pin to ?l? regardless of register values setup. in this case, all control register values are initilized. when all power management bits are ?0? in the 00h, 01h and 02h addresses, all blocks are powered-down. the register values will remain unchanged. power supply current is 18ua (typ) in this case. for fully shut down, the pdn pin should be ?l?. [ak4213] ms0949-e-01 - 33 - 2008/07 addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control 0 thdet 0 0 bype 0 sd3 sd2 sd1 r/w rd rd rd r/w rd r/w r/w r/w default 0 0 0 0 0 0 0 0 sd1: input mode setting of li n1/in1- and rin1/in1+ pins 0: single-ended mode (default) 1: differential mode sd2: input mode setting of li n2/in2- and rin2/in2+ pins 0: single-ended mode (default) 1: differential mode sd3: input mode setting of li n3/in3- and rin3/in3+ pins 0: single-ended mode (default) 1: differential mode bype: bypass mode enable 0: disable (default) 1: enable when bype bit is changeed from ?0? to ?1? at pmspk bit = ?1?, the ak4213 changes to bypass mode after the speaker amp is powered-down. when bype bit is changed from ?1? to ?0?, spk-amp starts operating according to the setting of pmspk bit after exiting bypass mode. thdet: thermal shutdown detection 0: normal operation (default) 1: thermal shutdown status addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lch headphone mixer 0 0 hplr3 hpll3 hplr2 hpll2 hplr1 hpll1 05h rch headphone mixer 0 0 hprr3 hprl3 hprr2 hprl2 hprr1 hprl1 06h speaker mixer 0 0 spkr3 spkl3 spkr2 spkl2 spkr1 spkl1 07h reserved 0 0 0 0 0 0 0 0 r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 input mixers: ( figure 7 ) 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h input volume #1 r1v3 r1v2 r1v1 r1v0 l1v3 l1v2 l1v1 l1v0 09h input volume #2 r2v3 r2v2 r2v1 r2v0 l2v3 l2v2 l2v1 l2v0 0ah input volume #3 r3v3 r3v2 r3v1 r3v0 l3v3 l3v2 l3v1 l3v0 0bh reserved 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 1 0 1 0 1 0 input volumes: default: 0db ( table 1 ) [ak4213] ms0949-e-01 - 34 - 2008/07 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch mode control 1 0 0 moff 0 pts1 pts0 0 0 r/w rd rd r/w rd r/w r/w rd rd default 0 0 0 0 0 0 0 0 pts1-0: headphone-amp mute on/off transition time default: ?00?, typ. 16.4ms ( table 16 ) moff0: soft transition for changing hpmtn bit 0: enable (default) 1: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh headphone pga control 0 hpz hpmtn hpga4 hpga3 hpga2 hpga1 hpga0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 0 0 1 hpga4-0: headphone-amp volume setting default: 19h; 0db ( table 13 ) hpmtn: headphone-amp mute 0: mute (default) 1: normal output hpz: headphone-amp pull-down control 0: ground mode (default) hpl/hpr pins are shorted to vss3. 1: hi-z mode hpl/hpr pins are pulled-down by 25k (typ) to vss3. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh speaker pga control 0 0 spga5 spga4 spga3 spga2 spga1 spga0 r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 spga5-0: speaker-amp volume setting default: 18h; 0db ( table 12 ) when pmspk bit is set to ?0?, reading and writing of spga5-0 bits are inhibited. when changing from pmspk bit = ?0? to pmspk bit = ?1?, spga volume becomes default value (0db) regardless of the setting of spga5-0 bits. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh alc mode control 1 0 0 ref5 ref4 ref3 ref2 ref1 ref0 r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 1 1 1 1 0 0 ref5-0: reference value at alc recovery operation default: 3ch; +18db ( table 10 ) [ak4213] ms0949-e-01 - 35 - 2008/07 addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h alc mode control 2 0 0 0 ztm1 ztm0 wtm2 wtm1 wtm0 r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 1 1 0 1 wtm2-0: alc recovery waiting period default: ?101?, 524.8ms (typ.) ( table 8 ) ztm1-0: alc zero crossing timeout period default: ?01?, 32.8ms (typ.) ( table 7 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h alc mode control 3 0 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lmth: alc limiter detection level / recovery wainting counter reset level default: ?0? ( table 5 ) rgain1-0: alc recovery gain step default: ?00?; 1 step ( table 9 ) lmat1-0: alc limiter att step default: ?00?; 1 step ( table 6 ) zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable when alc bit is set to ?1?, the alc operation is enabled. the initial value is ?0? (disable). addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h test 0 0 0 0 0 0 0 0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 write ?0? into the ?0? registers. [ak4213] ms0949-e-01 - 36 - 2008/07 system design figure 29 shows the system connection diagram for the ak4213. the evaluation board [akd4213] demonstrates the optimum layout, power supply arrangement and measurement results. top view power supply 2.6 3.6v 0.1 hpr lin3/in3- vcom rin1/in+ svdd lin1/in1- pvdd sda tvdd rvinn rvinp cp cn scl vss1 avdd mixo hpl rin3/in3+ spn vss2 spp rin2/in2+ pvee vss3 pdn test spin lin2/in2- 2.2 + 0.1 0.22 0.22 0.22 0.22 0.22 0.22 + 2.2 + 0.1 2.2 + 0.1 up headphone speaker 0.1 3.9 ? 3.9 ? analog input analog input analog input power supply 1.6 3.6v analog ground digital ground 10 + (note) (note) 10 0.1 power supply 3.0 5.5v figure 29. typical connection diagram notes: - these capacitors should use low esr(equivalent series resistance) over all temperature range. when these capacitors are polarized, the positive side s hould be connected cp pin or analog ground. - vss1, vss2, and vss3 should be connected to same analog ground plane. - a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be taken from the vcom pin. - ac coupling capacitor of 0.22 f should be connected to lin/rin pins to reduce pop noise at the power-up of the input volume block. [ak4213] ms0949-e-01 - 37 - 2008/07 package 29pin csp (3.0mm x 3.0mm, 0.5mm pitch, bga) top view bottom view 0.65 0.05 0.08 s s 5 4 3 1 2 e c d a b 2.96 0.05 f 2.96 0.05 4 2 1 3 x x x x b 0.50 0.23 a 0.30 0.05 0.05 ab s m b dc fe a 0.48 0.25 0.05 5 4 3 1 2 [ak4213] ms0949-e-01 - 38 - 2008/07 marking 4213 xxxx a 1 xxxx: date code (4 digit) pin #a1 indication revision history date (yy/mm/dd) revision reason page contents 08/05/19 00 first edition 08/07/09 01 spec change 3 ordering guide ak4213ec AK4213ECB 32 register definitions 01h, gddly bit was deleted. 37 package package plan was changed. black type. important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. |
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